Method and system for performance monitoring within a data processing system

ABSTRACT

A method and system are disclosed which monitor specified events among the number of events within a data processing system. The system of the present invention includes a software writable control register which specifies the events within the data processing system which are to be monitored, hardware for monitoring the specified events, and logic for detecting each occurrence of a specified event. In addition, the system of the present invention includes a number of counters which incrementally advance in response to an occurrence of a specified event, wherein, in response to a setting of the control register, at least one of the counters is programmed to incrementally advance in response to an overflow from a second counter. By selectively linking the counters in this manner, the maximum number of occurrences which may be counted by the counters may be dynamically altered.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates in general to a data processing system,and in particular to a method and system for performance monitoringwithin a data processing system. Still more particularly, the presentinvention relates to a method and system for counting events within adata processing system in which a plurality of counters may beselectively linked.

2. Description of the Related Art

Within state-of-the-art processors, facilities are often provided whichenable the processor to count occurrences of software-selectable eventsand to time the execution of processes within an associated dataprocessing system. These facilities are known as the performance monitorof the processor.

Events within the data processing system are counted by one or morecounters within the performance monitor. The operation of such countersis managed by a control register, which is comprised of a plurality ofbit fields. In general, both the control register and the counters arereadable and writable by software. Thus, by writing values to thecontrol register, a user may select the events within the dataprocessing system to be monitored and specify the conditions under whichthe counters are enabled.

The performance monitor has many applications which enable a user tooptimize the performance of a data processing system. For example,software engineers may utilize timing data from the performance monitorto optimize programs by relocating branch instructions and memoryaccesses. In addition, the performance monitor may be utilized to gatherdata about the access times to the data processing system's L1 cache, L2cache, and main memory. Utilizing this data, system designers mayidentify performance bottlenecks specific to particular software orhardware environments.

Because the number of occurrences of an event, such as a memory access,may be large, state-of-the-art performance monitors typically utilizelarge counters (e.g., 32-bit counters). In addition, because eachcounter counts occurrences of only a single event, state-of-the artperformance monitors utilize a number of counters to provide a broaddescription of system performance. Consequently, to provide thefunctionality of multiple large counters, the processor chip areaallocated to the performance monitor becomes large as the size andnumber of counters increases. Because the cost of processor fabricationrises concomitantly with a processor's die size, the additionalfunctionality provided by additional counters and increased counter sizeis often sacrificed due to economic considerations.

Consequently, it would be desirable to provide a method and system forcounting events within a data processing system which reduce the size ofa plurality of counters within a performance monitor without reducingthe maximum number of event occurrences which may be counted withoutoverflow.

SUMMARY OF THE INVENTION

It is therefore one object of the present invention to provide animproved data processing system.

It is another object of the present invention to provide an improvedmethod and system for performance monitoring within a data processingsystem.

It is yet another object of the present invention to provide an improvedmethod and system for counting events within a data processing system inwhich a plurality of counters may be selectively linked.

The foregoing objects are achieved as is now described. A method andsystem are disclosed which monitor specified events among the number ofevents within a data processing system. The system of the presentinvention includes a software writable control register which specifiesthe events within the data processing system which are to be monitored,hardware for monitoring the specified events, and logic for detectingeach occurrence of a specified event. In addition, the system of thepresent invention includes a number of counters which incrementallyadvance in response to an occurrence of a specified event, wherein, inresponse to a setting of the control register, at least one of thecounters is programmed to incrementally advance in response to anoverflow from a second counter. By selectively linking the counters inthis manner, the maximum number of occurrences which may be counted bythe counters may be dynamically altered.

The above as well as additional objectives, features, and advantages ofthe present invention will become apparent in the following detailedwritten description.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are setforth in the appended claims. The invention itself, however, as well asa preferred mode of use, further objectives and advantages thereof, willbest be understood by reference to the following detailed description ofan illustrative embodiment when read in conjunction with theaccompanying drawings, wherein:

FIG. 1 illustrates a data processing system utilizing the method andsystem of the present invention;

FIG. 2 depicts a block diagram of the processor utilized by the dataprocessing system illustrated in FIG. 1;

FIG. 3 illustrates a monitor mode control register (MMCR) utilized tomanage the plurality of counters depicted in FIG. 2; and

FIG. 4 depicts a detailed block diagram of the plurality of countersutilized by the present invention to count events within the dataprocessing system depicted FIG. 1.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

With reference now to the figures and in particular with reference toFIG. 1, there is illustrated a data processing system employing themethod and system of the present invention. As depicted, data processingsystem 10 includes processing unit 12, display device 14, keyboard 16,and mouse 18. As is well-known in the art, a user may input data to dataprocessing system 10 utilizing keyboard 16 or mouse 18. Data processingsystem 10 outputs data to a user via display device 14. Processing unit12 includes means for interfacing display device 14, keyboard 16, andmouse 18 to processor 30, which is illustrated in FIG. 2.

Referring to FIG. 2, there is depicted a block diagram of a processoremploying the method and system of the present invention. Asillustrated, processor 30 includes performance monitor 32, floatingpoint unit 40, fixed point unit 42, instruction processing unit 44,instruction flow unit 46, L1 cache 48, bus interface unit 50, andinternal bus 52. In a preferred embodiment of the present invention,processor 30 includes a pipelined processor capable of executingmultiple instructions in a single cycle, such as the PowerPC 620 RISCprocessor.

As depicted, performance monitor 32 includes event detection and countercontrol logic 34, control registers 36, and counters 38. In thepreferred embodiment illustrated in FIG. 2, counters 38, designatedPMC1-PMC4 (performance monitor counters 1-4), are 16-bit counters andcontrol registers 36, designated MMCR0 and MMCR1 (monitor mode controlregisters 0 and 1), are 32-bit registers. One skilled in the art willappreciate that the size of counters 38 and control registers 36 isdependant upon design considerations of processor 30, including thedesired functionality of performance monitor 32 and the chip areaavailable within processor 30.

With reference now to FIG. 3, there is illustrated a representation ofMMCR0 which controls the operation of counters PMC1 and PMC2. Asillustrated, MMCR0 is partitioned into a number of bit fields whosesettings select events to be counted, enable performance monitorinterrupts, and specify the conditions under which counting is enabled.MMCR1, which controls the operation of PMC3 and PMC4, is arrangedsimilarly.

As depicted, bits 0-4 and 18 of MMCR0 determine the scenarios underwhich PMC1 and PMC2 are enabled to count. By setting bits withappropriate software, a user may enable either or both PMC1 and PMC2, orenable PMC1 initially and enable PMC2 only after PMC1 becomes negative.Bits 5, 16, and 17 are utilized to control interrupts triggered by PMC1and PMC2. If an interrupt for a PMC is enabled, an interrupt isgenerated when the counter becomes negative (i.e., the most significantbit is a 1). Finally, bits 19-25 and bits 26-31 are utilized to selectthe events monitored by PMC1 and PMC2, respectively. Although PMC1 canmonitor 43 different events, and PMC2 can monitor 32 different events,each counter can monitor only one event at a time. According to themethod and system of the present invention, the events monitored by PMC1and PMC2 include not only events generated by units 40-50 of FIG. 2, butalso overflows from other PMCs among counters 38.

Referring now to FIG. 4, there is depicted a more detailed block diagramof counters 38 of FIG. 2. Each of PMC1-PMC4 has an associatedmultiplexer 80-86 and a 16-bit incrementer 88-94. In response to controlsignals 98-102 from event detection and counter control logic 34 of FIG.2, each of multiplexers 80-86 selects from among the plurality of inputevents the event specified by the bit field within MMCR0 or MMCR1 whichselects events for the multiplexer's associated counter. When a selectedevent occurs, the counter for which the event is selected isincrementally advanced by its associated 16-bit incrementer. If, forexample, the event selected for PMC1 as determined by bits 19-25 ofMMCR0 is the overflow from PMC2, PMC1 incrementally advances only whenPMC2 overflows. Consequently, when PMC1 and PMC2 are configured in thismanner, PMC1 and PMC2 form a 32-bit counter. Thus, by setting bitswithin MMCR0, a user may selectively determine the maximum number ofoccurrences counted by PMC1-PMC4 by linking two or more countertogether. If a selected event does not occur during a given processorcycle, the counter for which the event is selected remains unchanged forthe processor cycle. In the preferred embodiment depicted in FIG. 4,each counter may count overflows only from the preceding counter. Aswill be understood by one skilled in the art, in another embodiment ofthe present invention each PMC may count overflows from each of theother counters. For example, PMC1 could count overflows from PMC2, PMC3,or PMC4; PMC2 could count overflows from PMC1, PMC3, or PMC4, etc.

Returning to FIG. 2, performance monitor 32 monitors selected eventsgenerated by the activity of units 40-50 or overflows from PMC1-PMC4 andcounts the occurrences of the selected events utilizing counters 38. Forexample, a user may desire to utilize performance monitor 32 to analyzethe execution of software in order to design algorithms and taskschedules that execute efficiently. When evaluating softwareperformance, the access time to the various levels of the memoryhierarchy of data processing system 10 is often of interest in order toidentify the frequency of accesses which require over a particularnumber of cycles to complete.

To monitor access times to memory, the user first sets the appropriatebit fields within MMCR0 utilizing suitable software executed byprocessor 30. Setting bits 26-31 within MMCR0 instructs performancemonitor 32 to monitor accesses to L1 cache 48 and system memory, whichis accessed via bus interface unit 50. In addition, by setting otherbits within MMCR0, the user selects a threshold number of clock cyclesand instructs PMC2 to count the occurrences of accesses which requirelonger than the threshold number of cycles to complete. By setting bits19-25 of MMCR0 to select the overflow signal from PMC2 as the eventcounted by PMC1, the user links PMC1 and PMC2 to form a 32-bit counter.Finally, the user sets bit 17 of MMCR0 to disable the interruptgenerated when PMC2 becomes negative. Depending upon the application,the user may choose either to disable or enable the interrupt generatedwhen PMC1 becomes negative by setting bit 16 of MMCR0.

Upon execution of the software under analysis, performance monitor 32receives signals from L1 cache 48 and bus interface unit 50 via internalbus 52 which indicate accesses to memory. Event detection and countercontrol logic 34 determines from these signals which accesses requiremore than the threshold number of cycles to complete. Then, utilizingthe values of the bit fields within MMCR0, event detection and countercontrol logic 34 selects which events are counted among the plurality ofinputs to multiplexers 80 and 82 by transmitting control signals 96 and98. Thus, as determined by the bit values within MMCR0, PMC2 incrementsin response to memory accesses that require more than the thresholdnumber of cycles to complete and PMC1 counts overflows from PMC2. Whenthe performance analysis terminates at the completion of the softwareroutine or at a user-defined interrupt, PMC1 and PMC2 contain the 32-bitvalue of the number of memory accesses which required greater than thethreshold number of cycles to complete. Utilizing appropriate softwarecommands, a user may then read the count value stored in PMC1 and PMC2.

The method and system of the present invention enhance both thefunctionality and flexibility of the performance monitor. When themaximum number of occurrences of selected events is anticipated to beless than 2¹⁶, a user may configure the performance monitor to monitorup to four events within the data processing system. However, if thenumber of anticipated event occurrences would cause a single PMC tooverflow, a user may configure the performance monitor to count up to2⁶⁴ occurrences without overflow. Thus, the present invention providesboth the functionality of a large counter size and the flexibility ofmonitoring several events simultaneously, while reducing the chip areaallocated to the performance monitor.

While the invention has been particularly shown and described withreference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention.

I claim:
 1. A system for monitoring specified events among a pluralityof events within a data processing system, comprising:means forspecifying selected events among said plurality of events which are tobe monitored; means for monitoring said specified events; means fordetecting each occurrence of a specified event; and a plurality ofcounters which incrementally advance in response to an occurrence of aspecified event, wherein responsive to said means for specifyingselected events at least one other counter among said plurality ofcounters is interconnected to a first counter and programmed toincrementally advance in response to an overflow from said firstcounter.
 2. The system for monitoring events within a data processingsystem of claim 1, wherein said means for specifying selected events tobe monitored comprises a control register including a plurality of bits,wherein settings of particular bits among said plurality of bits withinsaid control register specify, for each of said plurality of counters,an event to be counted.
 3. The system for monitoring events within adata processing system of claim 1, wherein said plurality of countersare 16-bit counters.
 4. A processor comprising:a plurality of functionalunits for manipulating data which generate a plurality of events duringoperation of said processor; means for specifying selected events amongsaid plurality of events which are to be monitored; means for monitoringsaid specified events; means for detecting each occurrence of aspecified event; and a plurality of counters which incrementally advancein response to an occurrence of a specified event, wherein responsive tosaid means for specifying selected events at least one other counteramong said plurality of counters is interconnected to a first counterand programmed to incrementally advance in response to an overflow fromsaid first counter.
 5. The processor of claim 4, wherein said means forspecifying selected events to be monitored comprises a control registerincluding a plurality of bits, wherein settings of particular bits amongsaid plurality of bits within said control register specify, for each ofsaid plurality of counters, an event to be counted.
 6. The processor ofclaim 4, wherein said plurality of counters are 16-bit counters.
 7. Amethod of monitoring events within a data processing system including aplurality of counters, wherein each counter among said plurality ofcounters counts occurrences of a specified event within said dataprocessing system, said method comprising:specifying events to bemonitored within said data processing system, wherein one of saidspecified events is an overflow signal from a first counter among saidplurality of counters; monitoring said specified events within said dataprocessing system; in response to detecting an occurrence of aparticular specified event, incrementing said first counter; and inresponse to detecting an overflow from said first counter, incrementinga second counter, such that a maximum number of occurrences which may becounted by said plurality of counters is dynamically alterable.
 8. Themethod of monitoring events within a data processing system of claim 7,wherein said step of specifying selected events to be monitoredcomprises setting particular bits among a plurality of bits within acontrol register to specify, for each of said plurality of counters, anevent to be counted.